CORE STOP - Macro definitions to stop core activities and power saving
[Definitions automatically generated by otStudio]

Defines
#define	IDLE   while(1)
	Forever loop.
#define	HIBE   Hibernate()
	For lowest possible power dissipation, this state allows the internal supply (VDDINT) to be powered down, while keeping the I/O supply (VDDEXT) running.
#define	SLEEP   Sleep()
#define	DEEPS   DeepSleep()
#define	RES   Reset()
	System reset.

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Define Documentation

#define DEEPS   DeepSleep()

Asynchronous systems, such as the RTC, may still be running, but cannot access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode.

#define HIBE   Hibernate()

#define IDLE   while(1)

#define RES   Reset()

#define SLEEP   Sleep()

The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. When in the sleep mode, assertion of any interrupt causes the processor to sense the value of the bypass bit (BYPASS) in the PLL control register ( PLL_CTL ). If bypass is disabled, the processor transitions to the full on mode. If bypass is enabled, the processor transitions to the active mode.

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